    [Patent Literature 1] JP-2005-507212 A (WO 03/036902 A2)    [Patent Literature 2] JP 2005284749 A (US 2005/0240930 A1)
A microprocessor adopting a multi core configuration performs parallel processing of multiple tasks. In order to raise a processing efficiency, it is necessary to schedule the processing order so as to satisfy restrictions (so-called deadline) of the processing time specified to each task. The processing efficiency is decided by how to optimize such scheduling.
For example, Patent Literature 1 discloses a method to realize an efficient task assignment or distribution by using hash values when processing tasks belonging to multiple groups with a multi-core processor. Patent Literature 2 discloses a computer that defines previously an execution sequence of threads and classifies into a grain size that can be exclusively executed, thereby achieving an efficient parallel processing.
Each technology of Patent Literatures 1 and 2 increases an efficiency of assignment of tasks (threads) to each processor core. A task assigned to each processor core is processed sequentially in processing stages corresponding to each core (pipeline processing). However, all the instructions are not performed in all the processing stages. Part of the processing stages may be not performed depending on a kind of instruction. For example, Memory Access (MA) stage is not performed by an inter-register calculation instruction. When this point is taken into consideration, the stages of pipeline processing may have room to raise a processing efficiency.